1. Field of the Invention
The invention relates to a non-volatile semiconductor storage device, and particularly relates to programming of an NAND flash memory.
2. Description of Related Art
In the NAND memory, data programming or erasing is repetitively performed. Due to the deterioration of the charge maintaining characteristic resulting from the deterioration of the tunnel insulating film or a change in threshold value resulting from the charges captured by the tunnel insulating film, a bit error may occur. Patent Document 1 (Japanese Patent Publication No. 2010-152989) discloses mounting an error checking correction (ECC) circuit as a solution against such bit error. In addition, Patent Document 2 (Japanese Patent Publication No. 2008-165805) discloses an error correction solution for multi-bit data in an NAND flash memory where a memory cell storing multi-bit data. Furthermore, Patent Document 3 (Japanese Patent Publication No. 2010-79486) discloses a flash memory in which a physical block whose number of corrected errors is higher than a threshold value is labeled as a warning block and registered in a table. In addition, the priority of the warning block is lowered in data writing.